3.5.7 FlexBus Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Module signals
Register
access
FlexBus
Transfers
Peripheral
bridge 0
Crossbar
switch
Figure 3-26. FlexBus configuration
Table 3-37. Reference links to related information
Topic Related module Reference
Full description FlexBus FlexBus
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
NOTE
FlexBus module is not available in 88 QFN package
3.5.7.1
FlexBus clocking
The system provides a dedicated clock source to the FlexBus module's external
CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See
Clock Distribution for more details.
3.5.7.2
FlexBus signal multiplexing
The multiplexing of the FlexBus address and data signals is controlled by the port control
module. However, the multiplexing of some of the FlexBus control signals are controlled
by the port control and FlexBus modules. The port control module registers control
Memories and memory interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
92 NXP Semiconductors
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