NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
Address: 4006_1000h base + 2h offset = 4006_1002h
Bit 7 6 5 4 3 2 1 0
Read
COMPAREL
Write
Reset
0 0 0 0 0 0 0 0
EWM_CMPL field descriptions
Field Description
COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset
even if the (default) minimum refresh time is required.
23.3.4 Compare High Register (EWM_CMPH)
The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256
clocks time, for the CPU to refresh the EWM counter.
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
NOTE
The valid values for CMPH are up to 0xFE because the EWM
counter never expires when CMPH = 0xFF. The expiration
happens only if EWM counter is greater than CMPH.
Address:
4006_1000h base + 3h offset = 4006_1003h
Bit 7 6 5 4 3 2 1 0
Read
COMPAREH
Write
Reset
1 1 1 1 1 1 1 1
EWM_CMPH field descriptions
Field Description
COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset
even if the (default) maximum refresh time is required.
Memory Map/Register Definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
514 NXP Semiconductors