RCM_SRS1 field descriptions (continued)
Field Description
0
JTAG
JTAG Generated Reset
Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ,
and CLAMP.
0 Reset not caused by JTAG
1 Reset caused by JTAG
14.2.3 Reset Pin Filter Control register (RCM_RPFC)
NOTE
The reset values of bits 2-0 are for Chip POR only. They are
unaffected by other reset types.
NOTE
The bus clock filter is reset when disabled or when entering
stop mode. The LPO filter is reset when disabled .
Address:
4007_F000h base + 4h offset = 4007_F004h
Bit 7 6 5 4 3 2 1 0
Read 0
RSTFLTSS RSTFLTSRW
Write
Reset
0 0 0 0 0 0 0 0
RCM_RPFC field descriptions
Field Description
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
RSTFLTSS
Reset Pin Filter Select in Stop Mode
Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS
modes. On exit from VLLS mode, this bit should be reconfigured before clearing PMC_REGSC[ACKISO].
0 All filtering disabled
1 LPO clock filter enabled
RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes
Selects how the reset pin filter is enabled in run and wait modes.
00 All filtering disabled
01 Bus clock filter enabled for normal operation
10 LPO clock filter enabled for normal operation
11 Reserved
Chapter 14 Reset Control Module (RCM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 345
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