• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS)
signals
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse
width
48.1.2
Modes of operation
48.1.2.1 Stop mode
The LPUART will remain functional during Stop mode, provided the asynchronous
transmit and receive clock remains enabled. The LPUART can generate an interrupt or
DMA request to cause a wakeup from Stop mode.
48.1.2.2
Wait mode
The LPUART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
The transmitter and receiver will finish transmitting/receiving the current word.
48.1.2.3
Debug mode
The LPUART remains functional in debug mode.
48.1.3
Signal Descriptions
Signal Description I/O
LPUART_TX Transmit data. This pin is normally an
output, but is an input (tristated) in single
wire mode whenever the transmitter is
disabled or transmit direction is
configured for receive data.
I/O
Table continues on the next page...
Introduction
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1304 NXP Semiconductors
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