Chapter 33
Random Number Generator Accelerator (RNGA)
33.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
This chapter describes the random-number-generator accelerator RNGA, including a
programming model, functional description, and application information. Throughout this
chapter, the terms "RNG" and "RNGA" are meant to be synonymous.
33.1.1
Overview
RNGA is a digital integrated circuit capable of generating 32-bit random numbers. The
random bits are generated using shift registers with clocks derived from two free-running,
independent ring oscillators. The configuration of the shift registers ensures statistically
good data, that is, data that looks random. The oscillators, with their unknown
frequencies and independent phases, provide the means of generating the required
entropy needed to create random data. The random words generated by RNGA are loaded
into an output register (OR). RNGA is designed to generate an error interrupt (if not
masked), if OR is read and does not contain valid random data. OR contains valid
random data if the LVL field in the status register (SR) is 1.
It is important to note there is no known cryptographic proof showing this is a secure
method of generating random data. In fact, there may be an attack against this random
number generator if its output is used directly in a cryptographic application. The attack
is based on the linearity of the internal shift registers. Therefore, it is highly
recommended that this random data produced by this module be used as an entropy
source to provide an input seed to a NIST-approved pseudo-random-number generator
based on DES or SHA-1 and defined in NIST FIPS PUB 186-2 Appendix 3 and NIST
FIPS PUB SP 800-90.
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 751
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