NOTE
Before the last byte of master receive mode, TXAK must be set
to send a NACK after the last byte's transfer. Therefore, the
DMA must be disabled before the last byte's transfer.
NOTE
In 10-bit address mode transmission, the addresses to send
occupy 2–3 bytes. During this transfer period, the DMA must
be disabled because the C1 register is written to send a repeat
start or to change the transfer direction.
46.5
Initialization/application information
Module Initialization (Slave)
1. Write: Control Register 2
• to enable or disable general call
• to select 10-bit or 7-bit addressing mode
2. Write: Address Register 1 to set the slave address
3. Write: Control Register 1 to enable the I2C module and interrupts
4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
5. Initialize RAM variables used to achieve the routine shown in the following figure
Module Initialization (Master)
1. Write: Frequency Divider register to set the I2C baud rate (see example in
description of ICR)
2. Write: Control Register 1 to enable the I2C module and interrupts
3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4. Initialize RAM variables used to achieve the routine shown in the following figure
5. Write: Control Register 1 to enable TX
6. Write: Control Register 1 to enable MST (master mode)
7. Write: Data register with the address of the target slave (the LSB of this byte
determines whether the communication is master receive or transmit)
The routine shown in the following figure encompasses both master and slave I2C
operations. For slave operation, an incoming I2C message that contains the proper
address begins I2C communication. For master operation, communication must be
Chapter 46 Inter-Integrated Circuit (I2C)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1211
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