Chapter 4
Memory Map
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in one 32-bit contiguous memory space. This chapter describes the memory and
peripheral locations within that memory space.
4.2
System memory map
The following table shows the high-level device memory map. This map provides the
complete architectural address space definition for the various sections. Based on the
physical sizes of the memories and peripherals, the actual address regions used may be
smaller.
The system memory map includes address spaces that are intended for specific purposes.
• The two ICode regions (address < 0x2000_0000) mapped to the FlexBus space allow
code to be executed with maximum performance.
• There is an aliased region that maps a system address space to the Program flash
section. Flash region aliasing is specifically intended for references to read-only data
coefficients in the flash while still preserving a full Harvard memory organization in
the processor core supporting concurrent instruction fetches (for example, from
RAM) and data accesses (from flash via the aliased space).
• The bitbanding functionality supported by the processor core uses aliased regions
that map to the basic RAM and peripheral address spaces. This functionality maps
each 32-bit word of the aliased address space to a unique bit in the underlying RAM
or peripheral address space to support single-bit insert and extract operations from
the processor.
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 139
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