NXP Semiconductors K22F series - Page 140

Table 4-1. System memory map
System 32-bit Address Range Destination Slave Access
0x0000_0000–0x07FF_FFFF
1
Program flash and read-only data
(Includes exception vectors in first 1024 bytes)
All masters
0x0800_0000–0x0FFF_FFFF FlexBus Cortex-M4 core
(M0) only
0x1000_0000–0x17FF_FFFF Reserved —
0x1800_0000–0x1BFF_FFFF FlexBus Cortex-M4 core
(M0) only
0x1C00_0000–0x1FFF_FFFF
2
SRAM_L: Lower SRAM (ICODE/DCODE) All masters
0x2000_0000–0x200F_FFFF
2
SRAM_U: Upper SRAM bitband region All masters
0x2010_0000–0x21FF_FFFF Reserved –
0x2200_0000–0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core
only
0x2400_0000-0x2FFF_FFFF Reserved –
0x3000_0000-0x33FF_FFFF
1
Program Flash and read-only data Cortex-M4 core
only
0x3400_0000-0x3FFF_FFFF Reserved –
0x4000_0000–0x4007_FFFF Bitband region for peripheral bridge 0 (AIPS-Lite0) Cortex-M4 core &
DMA/EzPort
0x4008_0000–0x400F_EFFF Reserved –
0x400F_F000–0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core &
DMA/EzPort
0x4010_0000–0x41FF_FFFF Reserved –
0x4200_0000–0x42FF_FFFF Aliased to peripheral bridge (AIPS-Lite) bitband Cortex-M4 core
only
0x4300_0000–0x43FD_FFFF Reserved –
0x43FE_0000–0x43FF_FFFF Aliased to general purpose input/output (GPIO) bitband Cortex-M4 core
only
0x4400_0000–0x5FFF_FFFF Reserved –
0x6000_0000–0x9FFF_FFFF FlexBus (External Memory) All masters
0xA000_0000–0xDFFF_FFFF FlexBus (External Peripheral - Not executable) All masters
0xE000_0000–0xE00F_FFFF Private peripherals Cortex-M4 core
only
0xE010_0000–0xFFFF_FFFF Reserved –
1. This map provides the complete architectural address space definition for the flash. Based on the physical sizes of the
memories implemented for a particular device, the actual address regions used may be smaller. See Flash Memory Sizes
for details.
2. This range varies depending on amount of SRAM implemented for a particular device. See SRAM sizes for details.
NOTE
1. EzPort master port is statically muxed with DMA master
port. Access rights to AIPS-Lite peripheral bridge and
general purpose input/output (GPIO) module address space
is limited to the core, DMA and EzPort.
System memory map
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
140 NXP Semiconductors