PDB counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CHnDLY1
CHnDLY0
SC[LDOK]
Figure 38-5. Registers update with SC[LDMOD] = x1
38.4.5
Interrupts
PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The
following table summarizes the interrupts.
Table 38-3. PDB interrupt summary
Interrupt Flags Enable bit
PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and
SC[DMAEN] = 0
PDB Sequence Error Interrupt CHnS[ERRm] SC[PDBEIE] = 1
38.4.6 DMA
If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is
set. When DMA is enabled, the PDB interrupt is not issued.
38.5
Application information
Application information
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
888 NXP Semiconductors