NXP Semiconductors K22F series - DMA Controller Configuration

Table 3-19. DMA request sources - MUX 0 (continued)
Source
number
Source module Source description Async DMA
capable
47 Reserved —
48 PDB —
49 Port control module Port A Yes
50 Port control module Port B Yes
51 Port control module Port C Yes
52 Port control module Port D Yes
53 Port control module Port E Yes
54 Reserved —
55 Reserved —
56 Reserved —
57 Reserved —
58 LPUART0 Receive Yes
59 LPUART0 Transmit Yes
60 DMA MUX Always enabled
61 DMA MUX Always enabled
62 DMA MUX Always enabled
63 DMA MUX Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
3.3.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first four DMA channels. The
assignments are detailed at PIT/DMA Periodic Trigger Assignments .
3.3.9
DMA Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 77