Table 3-19. DMA request sources - MUX 0 (continued)
Source
number
Source module Source description Async DMA
capable
8 Reserved —
9 Reserved —
10 Reserved —
11 Reserved —
12 I
2
S0 Receive Yes
13 I
2
S0 Transmit Yes
14 SPI0 Receive
15 SPI0 Transmit
16 SPI1 Transmit or Receive
17 Reserved —
18 I
2
C0 —
19 I
2
C1 —
20 FTM0 Channel 0
21 FTM0 Channel 1
22 FTM0 Channel 2
23 FTM0 Channel 3
24 FTM0 Channel 4
25 FTM0 Channel 5
26 FTM0 Channel 6
27 FTM0 Channel 7
28 FTM1 Channel 0
29 FTM1 Channel 1
30 FTM2 Channel 0
31 FTM2 Channel 1
32 FTM3 Channel 0
33 FTM3 Channel 1
34 FTM3 Channel 2
35 FTM3 Channel 3
36 FTM3 Channel 4
37 FTM3 Channel 5
38 FTM3 Channel 6
39 FTM3 Channel 7
40 ADC0 — Yes
41 ADC1 — Yes
42 CMP0 — Yes
43 CMP1 — Yes
44 Reserved —
45 DAC0 —
46 DAC1 —
Table continues on the next page...
System modules
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
76 NXP Semiconductors
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