PDBx_DACINTCn field descriptions (continued)
Field Description
Enables the external trigger for DAC interval counter.
0 DAC external trigger input disabled. DAC interval counter is reset and counting starts when a rising
edge is detected on selected trigger input source or software trigger is selected and SWTRIG is
written with 1.
1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input
triggers the DAC interval trigger.
0
TOE
DAC Interval Trigger Enable
This bit enables the DAC interval trigger.
0 DAC interval trigger disabled.
1 DAC interval trigger enabled.
38.3.10 DAC Interval n register (PDBx_DACINTn)
Note: This register is internally buffered, and any values written to the register are
written to its internal buffer instead; in other words, the internal device bus does not write
directly to this register. The value in this register's internal buffer is loaded into this
register only after "1" is written to the SC[LDOK] bit.
Address:
4003_6000h base + 154h offset + (8d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTn field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
INT DAC Interval
Specifies the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when
the DAC interval counter is equal to the DACINT. Reading this field returns the value of internal register
that is effective for the current PDB cycle.
Chapter 38 Programmable Delay Block (PDB)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 881
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