NXP Semiconductors K22F series - Features Mode Selection (Ftmx_Mode)

FTMx_STATUS field descriptions (continued)
Field Description
0 No channel event has occurred.
1 A channel event has occurred.
1
CH1F
Channel 1 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
0
CH0F
Channel 0 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
39.3.10 Features Mode Selection (FTMx_MODE)
This register contains the global enable bit for FTM-specific features and the control bits
used to configure:
• Fault control mode and interrupt
• Capture Test mode
• PWM synchronization
• Write protection
• Channel output initialization
These controls relate to all channels within this module.
Address:
Base address + 54h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FAULTIE
FAULTM
CAPTEST
PWMSYNC
WPDIS
INIT
FTMEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
912 NXP Semiconductors