NXP Semiconductors K22F series - System Clock Divider Register 2 (SIM_CLKDIV2)

SIM_CLKDIV1 field descriptions (continued)
Field Description
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)
Address: 4004_7000h base + 1048h offset = 4004_8048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
USBDIV
USBFRAC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_CLKDIV2 field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–1
USBDIV
USB clock divider divisor
This field sets the divide value for the fractional clock divider when the MCGFLLCLK, or MCGPLLCLK, or
IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
0
USBFRAC
USB clock divider fraction
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK, or
MCGPLLCLK, or IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
Chapter 12 System Integration Module (SIM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 287