24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)
The time-out value of the watchdog must be set to a minimum of four watchdog clock
cycles. This is to take into account the delay in new settings taking effect in the watchdog
clock domain.
Address: 4005_2000h base + 6h offset = 4005_2006h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
TOVALLOW
Write
Reset
0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0
WDOG_TOVALL field descriptions
Field Description
TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles
of the watchdog clock.
24.7.5 Watchdog Window Register High (WDOG_WINH)
NOTE
You must set the Window Register value lower than the Time-
out Value Register.
Address:
4005_2000h base + 8h offset = 4005_2008h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WINHIGH
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDOG_WINH field descriptions
Field Description
WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is
defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when
the timer has reached a value greater than or equal to this window length. A refresh outside this window
resets the system or if IRQRSTEN is set, it interrupts and then resets the system.
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
532 NXP Semiconductors
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