22.3.34 TCD Control and Status (DMA_TCDn_CSR)
Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 15d
Bit 15 14 13 12 11 10 9 8
Read
BWC MAJORLINKCH
Write 0
Reset
x* x* x* x* x* x* x* x*
Bit
7 6 5 4 3 2 1 0
Read
DONE
ACTIVE
MAJORELI
NK
ESG DREQ INTHALF INTMAJOR START
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_CSR field descriptions
Field Description
15–14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE:
If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00 No eDMA engine stalls.
01 Reserved
10 eDMA engine stalls for 4 cycles after each R/W.
11 eDMA engine stalls for 8 cycles after each R/W.
13–12
Reserved
This field is reserved.
11–8
MAJORLINKCH
Major Loop Link Channel Number
If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel’s TCDn_CSR[START] bit.
7
DONE
Channel Done
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count
reaches zero. The software clears it, or the hardware when the channel is activated.
NOTE:
This bit must be cleared to write the MAJORELINK or ESG bits.
Table continues on the next page...
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 479
To Next Page
Loading...
Need help?
General
