• You need to always update these bits after unlocking within 256 bus clock
cycles. Failure to update these bits resets the system.
• Programmable time-out period specified in terms of number of WDOG clock cycles.
• Ability to test WDOG timer and reset with a flag indicating watchdog test.
• Quick test—Small time-out value programmed for quick test.
• Byte test—Individual bytes of timer tested one at a time.
• Read-only access to the WDOG timer—Allows dynamic check that WDOG
timer is operational.
NOTE
Reading the watchdog timer counter while running the
watchdog on the bus clock might not give the accurate
counter value.
• Windowed refresh option
• Provides robust check that program flow is faster than expected.
• Programmable window.
• Refresh outside window leads to reset.
• Robust refresh mechanism
• Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus
clock cycles.
• Count of WDOG resets as they occur.
• Configurable interrupt on time-out to provide debug breadcrumbs. This is followed
by a reset after 256 bus clock cycles.
24.3
Functional overview
Functional overview
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
520 NXP Semiconductors
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