Table 9-1. Debug Components Description (continued)
Module Description
The FPB also contains six instruction comparators for
matching against instruction fetches from Code space, and
remapping to a corresponding area in System space.
Alternatively, the six instruction comparators can individually
configure the comparators to return a Breakpoint Instruction
(BKPT) to the processor core on a match, so providing
hardware breakpoint capability.
TPIU (Trace Port Inteface Unit) Asynchronous Mode (1-pin) = TRACE_SWO (available on
JTAG_TDO)
9.1.1 References
For more information on ARM debug components, see these documents:
• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1
• ARM CoreSight Architecture Specification
9.2
The Debug Port
The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in
the following figure:
Chapter 9 Debug
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 201
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