USBx_ISTAT field descriptions (continued)
Field Description
In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake
phase of a USB transaction.This interrupt can be used to determine whether the last USB transaction was
completed successfully or stalled.
6
ATTACH
Attach Interrupt
This field is set when the USB Module detects an attach of a USB device. This field is only valid if
CTL[HOSTMODEEN]=1. This interrupt signifies that a peripheral is now present and must be configured; it
is asserted if there have been no transitions on the USB for 2.5 µs and the current bus state is not SE0."
0 No Attach is detected since the last time the ATTACH bit was cleared.
1 A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than
2.5 µs).
5
RESUME
This bit is set when a K-state is observed on the DP/DM signals for 2.5 µs. When not in suspend mode
this interrupt must be disabled.
4
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms. The sleep timer is
reset by activity on the USB bus.
3
TOKDNE
This bit is set when the current token being processed has completed. The processor must immediately
read the STATUS (STAT) register to determine the EndPoint and BD used for this token. Clearing this bit
(by writing a one) causes STAT to be cleared or the STAT holding register to be loaded into the STAT
register.
2
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
In Host mode this field is set when the SOF threshold is reached, so that software can prepare for the next
SOF.
1
ERROR
This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur. The
processor must then read the ERRSTAT register to determine the source of the error.
0
USBRST
This bit is set when the USB Module has decoded a valid USB reset. This informs the processor that it
should write 0x00 into the address register and enable endpoint 0. USBRST is set after a USB reset has
been detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been
removed and then reasserted.
43.4.10 Interrupt Enable register (USBx_INTEN)
Contains enable fields for each of the interrupt sources within the USB Module. Setting
any of these bits enables the respective interrupt source in the ISTAT register. This
register contains the value of 0x00 after a reset.
Address:
4007_2000h base + 84h offset = 4007_2084h
Bit 7 6 5 4 3 2 1 0
Read
STALLEN ATTACHEN RESUMEEN SLEEPEN TOKDNEEN SOFTOKEN ERROREN USBRSTEN
Write
Reset
0 0 0 0 0 0 0 0
USBx_INTEN field descriptions
Field Description
7
STALLEN
STALL Interrupt Enable
Table continues on the next page...
Chapter 43 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1091
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