USBx_USBTRC0 field descriptions (continued)
Field Description
This bit, when set, allows the USB module to send an asynchronous wakeup event to the MCU upon
detection of resume signaling on the USB bus. The MCU then re-enables clocks to the USB module. It is
used for low-power suspend mode when USB module clocks are stopped or the USB transceiver is in
Suspend mode. Async wakeup only works in device mode.
0 USB asynchronous wakeup from suspend mode disabled.
1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs
from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered
state of the D+ and D– pins. This interrupt should only be enabled when the Transceiver is
suspended.
4–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
USB_CLK_
RECOVERY_INT
Combined USB Clock Recovery interrupt status
This read-only field will be set to value high at 1'b1 when any of USB clock recovery interrupt conditions
are detected and those interrupts are unmasked.
For customer use the only unmasked USB clock recovery interrupt condition results from an overflow of
the frequency trim setting values indicating that the frequency trim calculated is out of the adjustment
range of the IRC48M output clock.
To clear this bit after it has been set, Write 0xFF to register USB_CLK_RECOVER_INT_STATUS.
1
SYNC_DET
Synchronous USB Interrupt Detect
0 Synchronous interrupt has not been detected.
1 Synchronous interrupt has been detected.
0
USB_RESUME_
INT
USB Asynchronous Interrupt
0 No interrupt was generated.
1 Interrupt was generated because of the USB asynchronous interrupt.
43.4.28 Frame Adjust Register (USBx_USBFRMADJUST)
Address: 4007_2000h base + 114h offset = 4007_2114h
Bit 7 6 5 4 3 2 1 0
Read
ADJ
Write
Reset
0 0 0 0 0 0 0 0
USBx_USBFRMADJUST field descriptions
Field Description
ADJ Frame Adjustment
In Host mode, the frame adjustment is a twos complement number that adjusts the period of each USB
frame in 12-MHz clock periods. A SOF is normally generated every 12,000 12-MHz clock cycles. The
Frame Adjust Register can adjust this by -128 to +127 to compensate for inaccuracies in the USB 48-MHz
clock. Changes to the ADJ bit take effect at the start of the next frame.
Memory map/Register definitions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1106 NXP Semiconductors
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