NXP Semiconductors K22F series - Flash Access Protection Register (FMC_PFAPR)

28.4.1 Flash Access Protection Register (FMC_PFAPR)
Address: 4001_F000h base + 0h offset = 4001_F000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved Reserved
Reserved
M2PFD M1PFD M0PFD
W
Reset
0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved M2AP[1:0] M1AP[1:0] M0AP[1:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
FMC_PFAPR field descriptions
Field Description
31–24
Reserved
This field is reserved.
23–20
Reserved
This field is reserved.
This read-only bitfield is reserved. Do not write to this bitfield or indeterminate results will occur.
19
Reserved
This field is reserved.
18
M2PFD
Master 2 Prefetch Disable
These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
17
M1PFD
Master 1 Prefetch Disable
These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Table continues on the next page...
Memory map and register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
600 NXP Semiconductors