• If CSCR[BLS] = 0, FB_AD from FB_AD31 downward
• If CSCR[BLS] = 1, FB_AD from FB_AD0 upward
31.4.5 Bit ordering
No bit ordering is required when connecting address and data lines to the FB_AD bus.
For example, a full 16-bit address/16-bit data device connects its addr15–addr0 to
FB_AD16–FB_AD1 and data15–data0 to FB_AD31–FB_AD16. See Data-byte
alignment and physical connections for a graphical connection.
31.4.6
Data transfer signals
Data transfers between FlexBus and the external memory or peripheral involve these
signals:
• Address/data bus (FB_AD31–FB_AD0 )
•
Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_R/W, FB_BEn)
• Attribute signals (FB_TBST, FB_TSIZ1–FB_TSIZ0)
31.4.7
Signal transitions
These signals change on the rising edge of the FlexBus clock (FB_CLK):
• Address
• Write data
• FB_TS/FB_ALE
• FB_CSn
• All attribute signals
FlexBus latches the read data on the rising edge of the clock.
31.4.8
Data-byte alignment and physical connections
The device aligns data transfers in FlexBus byte lanes with the number of lanes
depending on the data port width.
The following figure shows the byte lanes that external memory or peripheral connects to
and the sequential transfers of a 32-bit transfer for the supported port sizes when byte
lane shift is disabled. For example, an 8-bit memory connects to the single lane
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 705
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