FB_AD31–FB_AD24 (FB_BE_31_24). A 32-bit transfer through this 8-bit port takes
four transfers, starting with the LSB to the MSB. A 32-bit transfer through a 32-bit port
requires one transfer on each four-byte lane.
External
Data Bus
32-Bit Port
Memory
16-Bit Port
Memory
8-Bit Port
Memory
Byte Select
Byte 0
Byte 1
Byte 2
Byte 3
Byte 1 Byte 0
Byte 3 Byte 2
Byte 3 Byte 2 Byte 1 Byte 0
Driven with
address values
Driven with
address values
FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0]
FB_BE_7_0
FB_BE_15_8
FB_BE_23_16
FB_BE_31_24
In BLS = 0 mode, the byte enables always correspond to the same byte lanes,
regardless of which port size that you are using.
Figure 31-1. Connections for external memory port sizes (CSCRn[BLS] = 0)
The following figure shows the byte lanes that external memory or peripheral connects to
and the sequential transfers of a 32-bit transfer for the supported port sizes when byte
lane shift is enabled.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
706 NXP Semiconductors