43.4.4 Peripheral Additional Info register (USBx_ADDINFO)
Reads back the value of the Host Enable bit.
Address: 4007_2000h base + Ch offset = 4007_200Ch
Bit 7 6 5 4 3 2 1 0
Read 0 0 IEHOST
Write
Reset
0 0 0 0 0 0 0 1
USBx_ADDINFO field descriptions
Field Description
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
IEHOST
This bit is set if host mode is enabled.
43.4.5 OTG Interrupt Status register (USBx_OTGISTAT)
Records changes of the ID sense and VBUS signals. Software can read this register to
determine the event that triggers an interrupt. Only bits that have changed since the last
software read are set. Writing a one to a bit clears the associated interrupt.
Address:
4007_2000h base + 10h offset = 4007_2010h
Bit 7 6 5 4 3 2 1 0
Read Reserved ONEMSEC
LINE_
STATE_
CHG
0 Reserved Reserved 0 Reserved
Write w1c w1c
w1c
w1c w1c w1c
Reset
0 0 0 0 0 0 0 0
USBx_OTGISTAT field descriptions
Field Description
7
Reserved
This field is reserved.
Software should not change the value of this bitfield.
6
ONEMSEC
This bit is set when the 1 millisecond timer expires. This bit stays asserted until cleared by software. The
interrupt must be serviced every millisecond to avoid losing 1msec counts.
Table continues on the next page...
Memory map/Register definitions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1086 NXP Semiconductors
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