26.7.1.2 OSC_DIV (OSC_OSC_DIV)
OSC Clock divider register.
Address: 4006_5000h base + 2h offset = 4006_5002h
Bit 7 6 5 4 3 2 1 0
Read
ERPS
0 0 0 0 0 0
Write
Reset
0 0 0 0 0 0 0 0
OSC_OSC_DIV field descriptions
Field Description
7–6
ERPS
ERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output is
not affected by these two bits.
00 The divisor ratio is 1.
01 The divisor ratio is 2.
10 The divisor ratio is 4.
11 The divisor ratio is 8.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26.8 Functional Description
Functional details of the module can be found here.
26.8.1
OSC module states
The states of the OSC module are shown in the following figure. The states and their
transitions between each other are described in this section.
Chapter 26 Oscillator (OSC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 583
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