49.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 90h offset = 4002_F090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
FCONT
0
FPACK
0
FRSZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SYWD
0
MF FSE
ONDEM
FSP FSD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR4 field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
FCONT
FIFO Continue on Error
Configures when the SAI will continue receiving after a FIFO error has been detected.
0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been
cleared.
1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the
FIFO warning flag has been cleared.
27–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25–24
FPACK
FIFO Packing Mode
Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is greater than 8-
bit or 16-bit then only the first 8-bit or 16-bits are stored to the FIFO. The first word in each frame always
starts with a new 32-bit FIFO word and the first bit shifted must be configured within the first packed word.
When FIFO packing is enabled, the FIFO read pointer will only increment when the full 32-bit FIFO word
has been read by software.
00 FIFO packing is disabled
01 Reserved.
10 8-bit FIFO packing is enabled
11 16-bit FIFO packing is enabled
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1358 NXP Semiconductors
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