The digital glitch filter implemented in the IIC module, controlled by the
I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in
bus clock cycle counts.
3.9.4 UART Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
UART
Figure 3-54. UART configuration
Table 3-68. Reference links to related information
Topic Related module Reference
Full description UART UART
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.9.4.1 UART configuration information
This chip contains three UART modules. This section describes how each module is
configured on this device.
1. Standard features of all UARTs:
• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 131
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