UARTx_TWFIFO field descriptions
Field Description
TXWATER Transmit Watermark
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this register
field, an interrupt via S1[TDRE] or a DMA request via C5[TDMAS] is generated as determined by
C5[TDMAS] and C2[TIE]. For proper operation, the value in TXWATER must be set to be less than the
size of the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
47.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)
This is a read only register that indicates how many datawords are currently in the
transmit buffer/FIFO. It may be read at any time.
Address:
Base address + 14h offset
Bit 7 6 5 4 3 2 1 0
Read TXCOUNT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_TCFIFO field descriptions
Field Description
TXCOUNT Transmit Counter
The value in this register indicates the number of datawords that are in the transmit FIFO/buffer. If a
dataword is being transmitted, that is, in the transmit shift register, it is not included in the count. This
value may be used in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
transmit FIFO/buffer.
47.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)
This register provides the ability to set a programmable threshold for notification of the
need to remove data from the receiver FIFO/buffer. This register may be read at any time
but must be written only when C2[RE] is not asserted. Changing the value in this register
will not clear S1[RDRF].
Address:
Base address + 15h offset
Bit 7 6 5 4 3 2 1 0
Read
RXWATER
Write
Reset
0 0 0 0 0 0 0 1
Memory map and registers
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1246 NXP Semiconductors
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