I2Sx_TCR5 field descriptions (continued)
Field Description
greater than or equal to the word width when configured for MSB First. The value written must be less
than or equal to 31-word width when configured for LSB First.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
49.3.7 SAI Transmit Data Register (I2Sx_TDRn)
Address: 4002_F000h base + 20h offset + (4d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
TDR
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TDRn field descriptions
Field Description
TDR Transmit Data Register
The corresponding TCR3[TCE] bit must be set before accessing the channel's transmit data register.
Writes to this register when the transmit FIFO is not full will push the data written into the transmit data
FIFO. Writes to this register when the transmit FIFO is full are ignored.
49.3.8 SAI Transmit FIFO Register (I2Sx_TFRn)
The MSB of the read and write pointers is used to distinguish between FIFO full and
empty conditions. If the read and write pointers are identical, then the FIFO is empty. If
the read and write pointers are identical except for the MSB, then the FIFO is full.
Address:
4002_F000h base + 40h offset + (4d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 WFP
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 RFP
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1350 NXP Semiconductors
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