ADCx_CLMS field descriptions (continued)
Field Description
CLMS Calibration Value
Calibration Value
34.3.20 ADC Minus-Side General Calibration Value Register
(ADCx_CLM4)
For more information, see CLMD register description.
Address:
Base address + 5Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM4
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
ADCx_CLM4 field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLM4 Calibration Value
Calibration Value
34.3.21 ADC Minus-Side General Calibration Value Register
(ADCx_CLM3)
For more information, see CLMD register description.
Address:
Base address + 60h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ADCx_CLM3 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLM3 Calibration Value
Calibration Value
Chapter 34 Analog-to-Digital Converter (ADC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 787