28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)
The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and
the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
This section represents tag/vld information for all sets in the indicated way.
Address: 4001_F000h base + 120h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
tag[18:5]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
tag[18:5]
0
valid
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_TAGVDW1Sn field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–5
tag[18:5]
14-bit tag for cache entry
4–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
valid
1-bit valid for cache entry
Memory map and register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
608 NXP Semiconductors
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