42.2.4 RTC Time Compensation Register (RTC_TCR)
Address: 4003_D000h base + Ch offset = 4003_D00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CIC TCV
CIR TCR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_TCR field descriptions
Field Description
31–24
CIC
Compensation Interval Counter
Current value of the compensation interval counter. If the compensation interval counter equals zero then
it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a
second.
23–16
TCV
Time Compensation Value
Current value used by the compensation logic for the present second interval. Updated once a second if
the CIC equals 0 with the contents of the TCR field. If the CIC does not equal zero then it is loaded with
zero (compensation is not enabled for that second increment).
15–8
CIR
Compensation Interval Register
Configures the compensation interval in seconds from 1 to 256 to control how frequently the TCR should
adjust the number of 32.768 kHz cycles in each second. The value written should be one less than the
number of seconds. For example, write zero to configure for a compensation interval of one second. This
register is double buffered and writes do not take affect until the end of the current compensation interval.
TCR Time Compensation Register
Configures the number of 32.768 kHz clock cycles in each second. This register is double buffered and
writes do not take affect until the end of the current compensation interval.
80h Time Prescaler Register overflows every 32896 clock cycles.
... ...
FFh Time Prescaler Register overflows every 32769 clock cycles.
00h Time Prescaler Register overflows every 32768 clock cycles.
01h Time Prescaler Register overflows every 32767 clock cycles.
.... ...
7Fh Time Prescaler Register overflows every 32641 clock cycles.
Chapter 42 Real Time Clock (RTC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1055
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