11.5.1 Pin Control Register n (PORTx_PCRn)
NOTE
See the Signal Multiplexing and Pin Assignment chapter for the
reset value of this device.
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
that are not available in a reduced-pin package offering.
Unbonded pins not available in a package are disabled by
default to prevent them from consuming power.
Address:
Base address + 0h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 ISF 0
IRQC
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LK
0
MUX
0
DSE ODE PFE
0
SRE PE PS
W
Reset
0 0 0 0 * * * * 0 * 0 * 0 * * *
* Notes:
MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.•
PORTx_PCRn field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24
ISF
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
248 NXP Semiconductors
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