• Digital input filter for each pin, usable by any digital peripheral muxed onto the
pin
• Individual enable or bypass control field per pin
• Selectable clock source for digital input filter with a five bit resolution on filter
size
• Functional in all digital pin multiplexing modes
• Port control
• Individual pull control fields with pullup, pulldown, and pull-disable support
• Individual drive strength field supporting high and low drive strength
• Individual slew rate field supporting fast and slow slew rates
• Individual input passive filter field supporting enable and disable of the
individual input passive filter
• Individual open drain field supporting enable and disable of the individual open
drain output
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
six chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
11.2.2
Modes of operation
11.2.2.1 Run mode
In Run mode, the PORT operates normally.
11.2.2.2
Wait mode
In Wait mode, PORT continues to operate normally and may be configured to exit the
Low-Power mode if an enabled interrupt is detected. DMA requests are still generated
during the Wait mode, but do not cause an exit from the Low-Power mode.
11.2.2.3
Stop mode
In Stop mode, the PORT can be configured to exit the Low-Power mode via an
asynchronous wake-up signal if an enabled interrupt is detected.
In Stop mode, the digital input filters are bypassed unless they are configured to run from
the LPO clock source.
Overview
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
240 NXP Semiconductors
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