46.3.1 I2C Address Register 1 (I2Cx_A1)
This register contains the slave address to be used by the I2C module.
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read
AD[7:1]
0
Write
Reset
0 0 0 0 0 0 0 0
I2Cx_A1 field descriptions
Field Description
7–1
AD[7:1]
Address
Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is
used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
46.3.2 I2C Frequency Divider register (I2Cx_F)
Address: Base address + 1h offset
Bit 7 6 5 4 3 2 1 0
Read
MULT ICR
Write
Reset
0 0 0 0 0 0 0 0
I2Cx_F field descriptions
Field Description
7–6
MULT
Multiplier Factor
Defines the multiplier factor (mul). This factor is used along with the SCL divider to generate the I2C baud
rate.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
ICR ClockRate
Prescales the I2C module clock for bit rate selection. This field and the MULT field determine the I2C baud
rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values
corresponding to each ICR setting, see I2C divider and hold values.
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider)
Table continues on the next page...
Chapter 46 Inter-Integrated Circuit (I2C)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1185
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