NXP Semiconductors K22F series User Manual

Table 7-1. Chip power modes (continued)
Chip mode Description Core mode Normal
recovery
method
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
VLLS2 (Very
Low Leakage
Stop2)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Sleep Deep Wakeup Reset
2
VLLS1 (Very
Low Leakage
Stop1)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and 32-byte VBAT register file remain powered for
customer-critical data.
Sleep Deep Wakeup Reset
2
VLLS0 (Very
Low Leakage
Stop 0)
Most peripherals are disabled (with clocks stopped), but LLWU and
RTC can be used. NVIC is disabled; LLWU is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and 32-byte VBAT register file remain powered for
customer-critical data.
The POR detect circuit can be optionally powered off.
Sleep Deep Wakeup Reset
2
BAT (backup
battery only)
The chip is powered down except for the VBAT supply. The RTC and
the 32-byte VBAT register file for customer-critical data remain
powered.
Off Power-up
Sequence
1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
7.4 Entering and exiting power modes
The WFI instruction invokes wait and stop modes for the chip. The processor exits the
low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC)
describes interrupt operation and what peripherals can cause interrupts.
NOTE
The WFE instruction can have the side effect of entering a low-
power mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from
VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU
inputs" in the LLWU configuration section for a list of the sources.
Chapter 7 Power Management
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 187

NXP Semiconductors K22F series Specifications

General

Brand	NXP Semiconductors
Model	K22F series
Category	Controller
Language	English