3.9.5.1 LPUART0 overview
The LPUART0 module supports basic UART with DMA interface function and x4 to
x32 oversampling of baud-rate.
The module can remain functional in Stop and VLPS mode provided the clock it is using
remains enabled.
This module supports LIN slave operation.
3.9.6 I
2
S configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
2
I S
Figure 3-56. I
2
S configuration
Table 3-70. Reference links to related information
Topic Related module Reference
Full description >I
2
S I2S
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal multiplexing Port control Signal Multiplexing
3.9.6.1 Instantiation information
This device contains one I
2
S module.
As configured on the device, module features include:
• TX data lines: 1
• RX data lines: 1
Communication interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
134 NXP Semiconductors
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