• FIFO size (words): 8
• Maximum words per frame: 16
• Maximum bit clock divider: 512
3.9.6.2 I
2
S/SAI clocking
3.9.6.2.1 Audio Master Clock
The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.
3.9.6.2.2 Bit Clock
The I
2
S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter
product.
3.9.6.2.3
Bus Clock
The bus clock is used by the control registers and to generate synchronous interrupts and
DMA requests.
3.9.6.2.4
I
2
S/SAI clock generation
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects
the clock input to the I
2
S/SAI module’s MCLK divider.
The following table shows the input clock selection options on this device.
Table 3-71. I2S0 MCLK input clock selection
MCR[MICS] Clock Selection
00 System clock
01 OSC0ERCLK
10 Not supported
11 MCGPLLCLK, MCGFLLCLK, or IRC48MCLK
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 135
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