The module's MCLK Divide Register (MDR) configures the MCLK divide ratio.
The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE])
controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0,
and the pin is the output from the clock divider when MOE is 1.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock. Each module's Clocking Mode field of the
Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL]
and RCR2[MSEL]) selects the master clock.
The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for this
device.
Table 3-72. I2S0 master clock settings
TCR2[MSEL], RCR2[MSEL] Master Clock
00 Bus Clock
01 I2S0_MCLK
10 Not supported
11 Not supported
3.9.6.2.5 Clock gating and I
2
S/SAI initialization
The clock to the I
2
S/SAI module can be gated using a bit in the SIM. To minimize power
consumption, these bits are cleared after any reset, which disables the clock to the
corresponding module. The clock enable bit should be set by software at the beginning of
the module initialization routine to enable the module clock before initialization of any of
the I
2
S/SAI registers.
3.9.6.3
I
2
S/SAI operation in low power modes
3.9.6.3.1 Stop and very low power modes
In Stop mode, the SAI transmitter and/or receiver can continue operating provided the
appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively),
and provided the transmitter and/or receiver is/are using an externally generated bit clock
or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter
and/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.
Communication interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
136 NXP Semiconductors
To Next Page
Loading...
Need help?
General
