PORT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_D064 Pin Control Register n (PORTE_PCR25) 32 R/W See section 11.5.1/248
4004_D068 Pin Control Register n (PORTE_PCR26) 32 R/W See section 11.5.1/248
4004_D06C Pin Control Register n (PORTE_PCR27) 32 R/W See section 11.5.1/248
4004_D070 Pin Control Register n (PORTE_PCR28) 32 R/W See section 11.5.1/248
4004_D074 Pin Control Register n (PORTE_PCR29) 32 R/W See section 11.5.1/248
4004_D078 Pin Control Register n (PORTE_PCR30) 32 R/W See section 11.5.1/248
4004_D07C Pin Control Register n (PORTE_PCR31) 32 R/W See section 11.5.1/248
4004_D080 Global Pin Control Low Register (PORTE_GPCLR) 32
W
(always
reads 0)
0000_0000h 11.5.2/251
4004_D084 Global Pin Control High Register (PORTE_GPCHR) 32
W
(always
reads 0)
0000_0000h 11.5.3/251
4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.5.4/252
4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.5.5/252
4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.5.6/253
4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.5.7/253
Chapter 11 Port Control and Interrupts (PORT)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 247