NXP Semiconductors K22F series - Page 200

Private Peripheral Bus
(internal)
ITM
TPIU
Core
FPB
AHB-AP
NVIC
SWJ-DP
Bus
Matrix
APB
i/f
Trace port
(serial wire
or multi-pin)
Cortex-M4
SW/
JTAG
Debug
Sleep
Interrupts
INTNMI
SLEEPING
SLEEPDEEP
INTISR[239:0]
AWIC
ROM
Table
Instr. Data
MCM
I-code bus
D-code bus
System bus
Code bus
MDM-AP
DWT
Figure 9-1. Cortex-M4 Debug Topology
The following table presents a brief description of each one of the debug components.
Table 9-1. Debug Components Description
Module Description
SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG
AHB-AP AHB Master Interface from JTAG to debug module and SOC
system memory maps
MDM-AP Provides centralized control and status registers for an
external debugger to control the device.
ROM Table Identifies which debug IP is available.
Core Debug Singlestep, Register Access, Run, Core Status
ITM S/W Instrumentation Messaging + Simple Data Trace
Messaging + Watchpoint Messaging
DWT (Data and Address Watchpoints) 4 data and address watchpoints
FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code
and data from code space to system space.
The FPB unit contains two literal comparators for matching
against literal loads from Code space, and remapping to a
corresponding area in System space.
Table continues on the next page...
Introduction
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
200 NXP Semiconductors