Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
GPIO controller
Crossbar
switch
Transfers
Figure 3-57. GPIO configuration
Table 3-73. Reference links to related information
Topic Related module Reference
Full description GPIO GPIO
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Transfers Crossbar switch Clock Distribution
Signal Multiplexing Port control Signal Multiplexing
3.10.1.1 Number of GPIO signals
The number of GPIO signals available on the devices covered by this document are
detailed in Orderable part numbers .
Eight GPIO pins support a high drive capability - PTB0, PTB1, PTD4, PTD5, PTD6,
PTD7, PTC3, and PTC4. All other GPIO support normal drive option only.
PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE]
control. This reset default is to have this function disabled.
Human-machine interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
138 NXP Semiconductors
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