DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined 22.3.24/470
4000_91A8
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD13_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_91A8
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD13_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_91A8
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD13_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_91AC
TCD Last Source Address Adjustment
(DMA_TCD13_SLAST)
32 R/W Undefined 22.3.28/474
4000_91B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined 22.3.29/475
4000_91B4
TCD Signed Destination Address Offset
(DMA_TCD13_DOFF)
16 R/W Undefined 22.3.30/475
4000_91B6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD13_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_91B8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD13_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_91BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined 22.3.34/479
4000_91BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD13_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_91BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD13_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
4000_91C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined 22.3.22/469
4000_91C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined 22.3.23/469
4000_91C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined 22.3.24/470
4000_91C8
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD14_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_91C8
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD14_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_91C8
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_91CC
TCD Last Source Address Adjustment
(DMA_TCD14_SLAST)
32 R/W Undefined 22.3.28/474
4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 22.3.29/475
4000_91D4
TCD Signed Destination Address Offset
(DMA_TCD14_DOFF)
16 R/W Undefined 22.3.30/475
4000_91D6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD14_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_91D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
440 NXP Semiconductors