Table 3-47. CMP input connections
CMP Inputs CMP0 CMP1
IN0 CMP0_IN0 CMP1_IN0
IN1 CMP0_IN1 CMP1_IN1
IN2 CMP0_IN2 CMP1_IN2
IN3 CMP0_IN3 12-bit DAC0_OUT/CMP1_IN3
IN4 12-bit DAC1 Output/CMP0_IN4 —
IN5 VREF Output/CMP0_IN5 VREF Output/CMP1_IN5
IN6 Bandgap Bandgap
IN7 6b DAC0 Reference 6b DAC1 Reference
3.7.2.2 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the
references are connected as follows:
• VREF_OUT - V
in1
input
• VDD - V
in2
input
3.7.2.3
External window/sample input
Individual PDB pulse-out signals control each CMP Sample/Window timing.
3.7.2.4
CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when the
CMPx_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate
a compare sequence that must first enable the CMP and DAC prior to performing a CMP
operation and capturing the output. In this device, control for this two staged sequencing
is provided from the LPTMR. The LPTMR provides a single trigger output to all
implemented comparators. Through configuration of the CMPx_CR1[TRIGM] bits the
trigger can be used to trigger a single comparator or multiple comparators concurrently.
The LPTMR triggering output is always enabled when the LPTMR is enabled. The first
signal is supplied to enable the CMP and DAC and is asserted at the same time as the
TCF flag is set. The delay to the second signal that triggers the CMP to capture the result
of the compare operation is dependent on the LPTMR configuration. In Time Counter
mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter
mode with prescaler bypassed, the delay is 1/2 Prescaler clock period.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 105
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