NXP Semiconductors K22F series User Manual

SCL
SDA
D0
Data Byte
New Calling Address
XX
Calling Address
SDA
Calling Address
Read/
Write
XXX D7 D6 D5 D4 D3 D2 D1AD6 AD5
AD7
AD4
LSB
MSB
1
6
2
5
8
3
4
7
9
1
6
2
5
8
3
4
7
9
LSB
MSB
1
6
2
5
8
3
4
7
9
LSB
MSB
1
6
2
5
8
3
4
7
9
LSB
MSB
AD6 R/WAD3 AD2 AD1AD5AD7 AD4 AD6 R/WAD3 AD2 AD1AD5AD7 AD4
Read/
Write
Read/
Write
R/WAD3 AD2 AD1
SCL
Start
Signal
Ack
Bit
No
Ack
Bit
Stop
Signal
Start
Signal
Ack
Bit
Repeated
Start
Signal
No
Ack
Bit
Stop
Signal
Figure 46-2. I2C bus transmission signals
46.4.1.1
START signal
The bus is free when no master device is engaging the bus (both SCL and SDA are high).
When the bus is free, a master may initiate communication by sending a START signal.
A START signal is defined as a high-to-low transition of SDA while SCL is high. This
signal denotes the beginning of a new data transfer—each data transfer might contain
several bytes of data—and brings all slaves out of their idle states.
46.4.1.2
Slave address transmission
Immediately after the START signal, the first byte of a data transfer is the slave address
transmitted by the master. This address is a 7-bit calling address followed by an R/W bit.
The R/W bit tells the slave the desired direction of data transfer.
• 1 = Read transfer: The slave transmits data to the master
• 0 = Write transfer: The master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master
responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling
SDA low at the ninth clock.
Chapter 46 Inter-Integrated Circuit (I2C)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1197

NXP Semiconductors K22F series Specifications

General

Brand	NXP Semiconductors
Model	K22F series
Category	Controller
Language	English