UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A004 UART Status Register 1 (UART0_S1) 8 R C0h 47.3.5/1229
4006_A005 UART Status Register 2 (UART0_S2) 8 R/W 00h 47.3.6/1232
4006_A006 UART Control Register 3 (UART0_C3) 8 R/W 00h 47.3.7/1234
4006_A007 UART Data Register (UART0_D) 8 R/W 00h 47.3.8/1235
4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h 47.3.9/1236
4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h
47.3.10/
1237
4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 00h
47.3.11/
1237
4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h
47.3.12/
1238
4006_A00C UART Extended Data Register (UART0_ED) 8 R 00h
47.3.13/
1239
4006_A00D UART Modem Register (UART0_MODEM) 8 R/W 00h
47.3.14/
1240
4006_A00E UART Infrared Register (UART0_IR) 8 R/W 00h
47.3.15/
1241
4006_A010 UART FIFO Parameters (UART0_PFIFO) 8 R/W See section
47.3.16/
1242
4006_A011 UART FIFO Control Register (UART0_CFIFO) 8 R/W 00h
47.3.17/
1243
4006_A012 UART FIFO Status Register (UART0_SFIFO) 8 R/W C0h
47.3.18/
1244
4006_A013 UART FIFO Transmit Watermark (UART0_TWFIFO) 8 R/W 00h
47.3.19/
1245
4006_A014 UART FIFO Transmit Count (UART0_TCFIFO) 8 R 00h
47.3.20/
1246
4006_A015 UART FIFO Receive Watermark (UART0_RWFIFO) 8 R/W 01h
47.3.21/
1246
4006_A016 UART FIFO Receive Count (UART0_RCFIFO) 8 R 00h
47.3.22/
1247
4006_A018 UART 7816 Control Register (UART0_C7816) 8 R/W 00h
47.3.23/
1247
4006_A019 UART 7816 Interrupt Enable Register (UART0_IE7816) 8 R/W 00h
47.3.24/
1249
4006_A01A UART 7816 Interrupt Status Register (UART0_IS7816) 8 R/W 00h
47.3.25/
1250
4006_A01B UART 7816 Wait Parameter Register (UART0_WP7816) 8 R/W 00h
47.3.26/
1252
4006_A01C UART 7816 Wait N Register (UART0_WN7816) 8 R/W 00h
47.3.27/
1252
4006_A01D UART 7816 Wait FD Register (UART0_WF7816) 8 R/W 01h
47.3.28/
1253
Table continues on the next page...
Memory map and registers
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1220 NXP Semiconductors
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