47.4.2.6 Receiving break characters
The UART recognizes a break character when a start bit is followed by eight, nine, or ten
logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character
has these effects on UART registers:
• Sets the framing error flag, S1[FE].
• Writes an all 0 dataword to the data buffer, which may cause S1[RDRF] to set,
depending on the watermark and number of values in the data buffer.
• May set the overrun flag, S1[OR], noise flag, S1[NF], parity error flag, S1[PE], or
the receiver active flag, S2[RAF].
The detection threshold for a break character can be adjusted when using an internal
oscillator in a LIN system by setting S2[LBKDE]. The UART break character detection
threshold depends on C1[M], C1[PE], S2[LBKDE] and C4[M10]. See the following
table.
Table 47-7. Receive break character detection threshold
LBKDE M M10 PE Threshold (bits)
0 0 — — 10
0 1 0 — 11
0 1 1 1 12
1 0 — — 11
1 1 — — 12
While S2[LBKDE] is set, it will have these effects on the UART registers:
• Prevents S1[RDRF], S1[FE], S1[NF], and S1[PF] from being set. However, if they
are already set, they will remain set.
• Sets the LIN break detect interrupt flag, S2[LBKDIF], if a LIN break character is
received.
Break characters are not detected or supported when C7816[ISO_7816E] is set/enabled.
47.4.2.7
Hardware flow control
To support hardware flow control, the receiver can be programmed to automatically
deassert and assert RTS.
Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1273
To Next Page
Loading...
