Table 48-1. Break character length
BRK13 M M10 SBNS Break character
length
0 0 0 0 10 bit times
0 0 0 1 11 bit times
0 1 0 0 11 bit times
0 1 0 1 12 bit times
0 X 1 0 12 bit times
0 X 1 1 13 bit times
1 0 0 0 13 bit times
1 0 0 1 13 bit times
1 1 0 0 14 bit times
1 1 0 1 14 bit times
1 X 1 0 15 bit times
1 X 1 1 15 bit times
48.3.2.2 Hardware flow control
The transmitter supports hardware flow control by gating the transmission with the value
of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS
is asserted. If CTS is deasserted in the middle of a transmission with characters remaining
in the receiver data buffer, the character in the shift register is sent and LPUART_TX
remains in the mark state until CTS is reasserted.
If the clear-to-send operation is disabled, the transmitter ignores the state of CTS.
The transmitter's CTS signal can also be enabled even if the same LPUART receiver's
RTS signal is disabled.
48.3.2.3
Transceiver driver enable
The transmitter can use LPUART_RTS as an enable signal for the driver of an external
transceiver. See Transceiver driver enable using LPUART_RTS for details. If the
request-to-send operation is enabled, when a character is placed into an empty transmitter
data buffer, LPUART_RTS asserts one bit time before the start bit is transmitted.
LPUART_RTS remains asserted for the whole time that the transmitter data buffer has
any characters. LPUART_RTS deasserts one bit time after all characters in the
transmitter data buffer and shift register are completely sent, including the last stop bit.
Transmitting a break character also asserts LPUART_RTS, with the same assertion and
deassertion timing as having a character in the transmitter data buffer.
Chapter 48 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1325
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