51.1.3.1 Reset
The JTAGC block is placed in reset when either power-on reset is asserted, or the TMS
input is held high for enough consecutive rising edges of TCK to sequence the TAP
controller state machine into the Test-Logic-Reset state. Holding TMS high for five
consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state
regardless of the current TAP controller state. Asserting power-on reset results in
asynchronous entry into the reset state. While in reset, the following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the
test logic and allowing normal operation of the on-chip system logic to continue
unhindered
• The instruction register is loaded with the IDCODE instruction
51.1.3.2 IEEE 1149.1-2001 defined test modes
The JTAGC block supports several IEEE 1149.1-2001 defined test modes. A test mode is
selected by loading the appropriate instruction into the instruction register while the
JTAGC is enabled. Supported test instructions include EXTEST, HIGHZ, CLAMP,
SAMPLE and SAMPLE/PRELOAD. Each instruction defines the set of data register(s)
that may operate and interact with the on-chip system logic while the instruction is
current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the
EXTEST, SAMPLE or SAMPLE/PRELOAD instructions are active. The single-bit
bypass register shift stage is enabled for serial access between TDI and TDO when the
BYPASS, HIGHZ, CLAMP or reserved instructions are active. The functionality of each
test mode is explained in more detail in JTAGC block instructions.
51.1.3.3
Bypass mode
When no test operation is required, the BYPASS instruction can be loaded to place the
JTAGC block into bypass mode. While in bypass mode, the single-bit bypass shift
register is used to provide a minimum-length serial path to shift data between TDI and
TDO.
Chapter 51 JTAG Controller (JTAGC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1385
To Next Page
Loading...
Need help?
General
