reset is deasserted. EzPort mode can be disabled by programming the
FOPT[EZPORT_DIS] field in the Flash Memory module.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. What happens next depends on the NMI input and the
FOPT[NMI_DIS] field in the Flash Memory module:
• If the NMI input is high or the NMI function is disabled in the NMI_DIS field,
the CPU begins execution at the PC location.
• If the NMI input is low and the NMI function is enabled in the NMI_DIS field,
this results in an NMI interrupt. The processor executes an Exception Entry and
reads the NMI interrupt handler address from vector-table offset 8. The CPU
begins execution at the NMI interrupt handler.
Subsequent system resets follow this same reset flow.
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K22F Sub-Family Reference Manual, Rev. 4, 08/2016
180 NXP Semiconductors
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